MODELING AND CHARACTERIZATION OF PHYANALOG COMPONENTS ON BUS SYSTEM

MODELING AND CHARACTERIZATION OF PHYANALOG COMPONENTS ON BUS SYSTEM

Today's modern digital society confronts the car manufacturers with new challenges. The modern production of the vehicles on one hand and the intelligent and networked vehicle systems, on the other hand, require new data communication standards. The mechanical control of the individual systems in the vehicle has almost entirely been replaced by electronic systems, which are networked with each another. Depending on e.g. transmission speed, error tolerance, cost and system robustness, various communication systems and network structures can be used for data transmission [1]. The well-known bus systems are CAN-FD, LVDS, MOST, FlexRay and automotive Ethernet. The IP-based Ethernet technology standardized in IEEE 802.3 defines the requirements of the first and second layers of the OSI layer model. The stated standard is to be adapted and optimized for use in the vehicle [2]. Figure 1 shows the reference model (OSI model) for network protocols as a layered architecture.

This paper is organized as follows. In section II the two Ethernet standards for automotive communication, i.e. IEEE 802.3bw Standard and IEEE 802.3bp standard are briefly explained. Section III describes the requirements of the physical layer and the transmission channel. To design and simulate the Ethernet bus systems, 100 Mbit/s and 1000 Mbit/s, the models of their analog frontends are required. The model of the transceiver, low pass filter (LPF), common mode choke and common mode termination are presented in section IV. The models are verified by measurements

To increase transmission reliability, reduce costs and susceptibility to interference the current Fast Ethernet system, 1000Base-T1, has been defined. As described in [2], all individual components of the transmission system should be examined regarding the EMC requirements. Each component is to be verified and optimized individually and as a part of the whole system in vehicle level. For system developments and investigations, the equivalent circuit diagrams of the individual components are to be designed and verified by measurements. The modeling of such equivalent circuit diagrams becomes more and more difficult as the frequency increases. Therefore, the RF behavior of all components and components must be considered. According to specifications and definitions of Ethernet bus systems, an optimized interface network (OPT-BIN) consists of transceiver circuit, low pass filters, Common mode choke, DC block capacitors and common mode termination (Fig. 3). Figure 4 shows the simple SPICE equivalent circuit diagram for such an OPT-BIN. In the following sections, the individual blocks/components and their requirements are discussed in detail.

A.Modeling and characterization of the transceiver circuit A PHY chip for Automotive Ethernet assumes the role of full-duplex communication between two nodes while simultaneously preparing the data for digital signal processing. 100BASE-T1 and 1000BASE-T1 Ethernet PHYs enable the implementation of electronic architectures such as advanced driver assistance systems (ADAS). Modeling the equivalent PHY circuit for full-duplex transmission over twisted lines includes the transmitter and the receiver on each side of the channel

Bus Pass System

  The transmitted and received signals are to be separated by an echo cancellation circuit in each transceiver. Figure 5 shows the equivalent circuit of the transceiver developed in SPICE simulation tool. For the series production of transceiver chip in motor vehicles, certain EMC requirements and standards must be met. For example, the release of PHYs requires the following EMC tests with predefined limits. Based on the "Direct Power Injection (DPI)" test, the immunity of the system is examined. The interference emission of the PHY should be examined by means of the 150-ohm test method. One of the other mandatory tests is the study of spectral power density (PSD). The predefined masks for 100BASE-T1 and 1000BASE-T1 are shown in Fig. 6 using the blue and green lines. This figure illustrates the simulation results of the ideal transceiver circuit concerning the PSD masks and confirms the equivalent circuit model. The transceiver was fed by a PAM-3 Pseudo Random Binary Sequence (PRBS) data stream. This data was generated by MATLAB and imported into the SPICE model.

B. Modeling and Characterization of the Low Pass Filter The corresponding signal bandwidths for 100Base-T1 are 33.3 MHz and for the 1000Base-T1 standard about 375-400 MHz. Consequently, the operation of the LP filter shown in Fig.2 should be adjusted so that the pass-band of the filter covers the mentioned frequencies. Figure 7 shows the high-frequency equivalent circuit of the LP filter. Figure 8 shows the manufactured and assembled LPF-PCB. The values of the individual components were calculated separately for both Ethernet standards. They are shown in table I. In order to verify the model, the transmission behavior of the LP filter for both high-speed Ethernet standards is simulated and measured.

C.Modeling and characterization of the common mode Choke The differential mode (DM) signaling has the advantage of being relatively well protected against environmental noise. Asymmetry of the cable wires or adapters [7] and injected interferences can lead to common mode (CM) noise as well as differential mode signals on the data lines. To suppress the CM noise, a common mode choke (CMC) is inserted between the channel and the PHY, so that the unwanted CM signals are significantly attenuated. The increasing bandwidth requirements bring the CMCs e.g. due to tolerance requirements to their limits. In a previous work [11] the CMC of 100 Mbit/s was investigated. In this section, two CMCs required for 100Base-T1 and 1000BASE-T1 Ethernet communication in the automotive are compared and evaluated regarding their high-frequency characteristics using mixed mode S-parameters. Furthermore, CM and DM impedance of the chokes are studied and characterized. Figure 10 shows the used SPICE equivalent circuit diagram of the choke [11]. The parameters of the simulation model have been extracted from measurement results. https://codeshoppy.com/android-projects-titles-ieee.html

The model contains all parasitic effects including packaging, mounting and soldering effects. The associated values are shown in table I. Figure 11 shows the manufactured CMC boards for both Standards. Considering the different measurement structures for the DM and CM impedance [11], the equivalent circuit model was simulated. The simulation and measurement results of both standards are shown in Figure 12a and 12b. The comparison of the simulation results with the measurement results shows a good agreement. Code ShoppyTo evaluate mode conversion, insertion loss and return loss for differential data lines, mixed-mode scattering parameters (S-parameters) are used. 

D.Modeling and characterization of the common mode termination The last component of the transmission path is the common-mode termination. It consists of DC block capacitors with a value of 100 nF. They ensure that no DC current from PHY enters the channel. In addition, two parallel resistors between plus and minus path will be included. They have a value of 1kohm and are high-impedance termination. At the end, the high-impedance termination is provided by a resistor with a value of 100kohm and a capacitor with a value of 4.7 nF, which effectively blocks the unwanted frequencies.